IEC 61523-1 Ed. 3.0:2023 (en)
遅れ及び出力計算規格－第1部：集積回路 (IC) オープンライブラリアーキテクチャ (OLA)
Delay and power calculation standards - Part 1: Integrated Circuit (IC) Open Library Architecture (OLA)
発行年月日：
2023-10-11
状態：
有効
邦訳版：
無
英語 640ページ
86,625 円（税込） 本体価格：78,750円
- 規格概要
-
IEC 61523-1:2023 focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.全文を表示する
The standard specifications covered in this document are as follows:
- Description language for timing and power modeling, called the delay calculation language (DCL)
- Software procedural interface (PI) for communications between EDA applications and compiled libraries of DCL descriptions
- Standard file exchange format for parasitic information about the chip design: Standard Parasitic Exchange Format (SPEF)
- Informative usage examples
- Informative notes.
This is an IEC/IEEE dual logo standard.
| TC |
TC 91 |
|---|---|
| ICS |
35.060 |
| 備考 |
