JEITA EDR-7320
Design guideline of integrated circuits for Small Outline Package (SOP)
Date Published:
1998-12-01
Status:
Valid
Japanese:
Japanese 20pages
JPY 6,000 ( JPY 6,000excl. tax )
- Standard Abstract
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This technical report is about the design guideline of integrated circuits for small outline package (SOP).More
| ICS | |
|---|---|
| Corresponding Standards |
Explanation of Equivalency
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| Referenced JIS Stantards | |
| Referenced Stantards | |
| Remarks | Former No. ED-7402-1 |